RISC-V Enters the Era of Autonomous Control: KINGBROTHER IPDM Accelerates Hardware Productization

"15th Five-Year Plan" has written RISC-V into the national strategy. Chips and ecosystem are in place, but the real test lies in productization. KINGBROTHER leverages its one-stop Integrated Product Design and Manufacturing (IPDM) capabilities to accelerate large-scale deployment of RISC-V hardware.

Data source: Public industry reports and conference information

RISC-V Moves from "Alternative" to National Strategy

On September 15, 2026, the Ministry of Industry and Information Technology and the National Development and Reform Commission jointly issued the 15th Five-Year Plan for the Electronic Information Manufacturing Industry, listing "advancing the R&D and industrialization of the fifth-generation reduced instruction set computer (RISC-V)" as a key task, with explicit support for RISC-V chip applications in AI, embedded systems, and other fields.

As the computing center of gravity shifts from PCs and smartphones to robots, edge AI, and physical intelligent terminals, RISC-V now stands at the starting line to compete on the same stage as mainstream architectures. Through an open, free, and modular processor instruction set standard, it enables heterogeneous integration of real-time control cores and high-compute AI cores on a single chip. It returns the initiative of chip design innovation to every developer, naturally fitting the new generation of "autonomous + customizable" hardware requirements.

Hardware Engineering Complexity Moves Up a Level

The value of RISC-V is being redefined across different scenarios. It makes "architecture autonomy" possible, but also significantly raises the corresponding engineering difficulty:

Upfront redesign at the R&D end — Compute scales from MCU-level to 560T local deployment; architecture evolves from homogeneous to heterogeneous "real-time core + AI core" integration. The substitution logic has upgraded from swapping one chip to full-stack coordination of OS, drivers, toolchain, and device certification. Reference designs, schematics, BOMs, and SDKs must be built from scratch, and EMC and industry certifications must be moved upfront to the design stage.

Multiple constraints stack up on the manufacturing side — LPDDR5, PCIe, and SerDes force laminate loss to keep decreasing; high speed, high density, and high heat all press onto the same board. Domestic SoCs iterate rapidly, with long-lead materials facing dual volatility in lead time and price; alternative parts require secondary validation. Component selection must simultaneously satisfy "available for purchase" and "feasible to manufacture."

Raised standards on verification and delivery — Test specifications, fixtures, and use cases need to be rebuilt for the new platform. DFT/DFM, low-volume high-mix delivery, and one-stop service capabilities become key to successful RISC-V hardware product deployment.

KINGBROTHER's Scenario Products and IPDM Solutions

Built on the dual open-source architecture of domestic RISC-V and OpenHarmony, KINGBROTHER delivers solution design and productization capabilities covering the full compute range from 1T to 560T, together with one-stop IPDM (Integrated Product Design and Manufacturing) services including PCB and integrated manufacturing.

AIoT Smart Terminals

Scenario Positioning — Massive-connection devices such as smart control panels and edge gateways have stringent requirements for cost, power consumption, and size. Entry-level autonomous-controllable RISC-V SoCs offer a competitive high-efficiency solution.

Delivery Product Forms — Low-power core modules, AIoT edge gateways.

Smart Edge

Scenario Positioning — Targeted at edge boxes, smart analytics stations, and other edge computing devices. A single device must concurrently handle multi-channel video decoding and local AI inference workloads. RISC-V SoCs integrate multi-channel hardware video engines (typically supporting 32-channel 1080P decoding), with advantages of autonomous control and high cost-effectiveness, suitable for edge-side video analytics.

Delivery Product Forms — Edge computing boxes, industrial PCs.

AI Workstation / AI PC

Scenario Positioning — Targeted at AI workstations, AI PCs, edge servers, and other terminal scenarios with 100–560T compute range, supporting local large models and VLA multimodal inference. The core of this scenario is not a single AI accelerator chip, but a full-chain autonomous, high-compute hardware base.

Delivery Product Forms — Edge computing appliances, AI all-in-one machines, AI PC motherboards and complete systems.

Embodied Intelligence

Scenario Positioning — Targeted at humanoid robots, multi-form embodied robots, and other terminal scenarios requiring concurrent real-time motion control and local AI inference. The real-time core provides multi-channel CAN-FD/EtherCAT buses with microsecond-level response; the AI core delivers 60+ TOPS of compute, supporting RVV vector extensions for perception acceleration, meeting the integrated needs of robot motion control, environmental perception, and autonomous decision-making.

Delivery Product Forms — Main control boards, motion control boards, and core modules for humanoid / quadruped robots.

KINGBROTHER IPDM Service Advantages

Leveraging 29 years of one-stop IPDM (Integrated Product Design and Manufacturing) service system and RISC-V ecosystem advantages, KINGBROTHER provides full-chain technical services from design to manufacturing for RISC-V hardware products across more scenarios.

In hardware design, solutions can be customized according to scenario needs, with compute covering the full range from 1T to 560T, supporting entry-level modules to hundred-watt workstations. In manufacturing and supply chain, we connect PCB prototyping, components, complete device manufacturing, and reliability verification, reducing customer coordination costs and mass production risks. We offer mid-to-high-end PCBs including HDI and flex-rigid boards, specializing in thick-copper high-current and high-speed high-frequency processes, with CNAS-accredited laboratories and IPDM service bases nationwide.

In addition, KINGBROTHER maintains long-term collaboration with domestic RISC-V chip, algorithm, and complete machine ecosystems. Together with leading industry chain partners, we build a complete ecosystem loop covering "chip IP, AI compute, edge inference, cloud-scale compute, and complete device manufacturing," rapidly converting upstream chip platforms into mass-producible complete machine capabilities.

Customer Case: RISC-V Smart Analytics Station

The customer is a domestic chip design company aiming to build a smart analytics station for smart classroom and conference scenarios based on its self-developed RISC-V AI chip — requiring simultaneous multi-channel video capture and AI analysis, while operating stably under low power and small form factor constraints. KINGBROTHER primarily undertook the 0-to-1 engineering implementation of the complete device, providing PCB prototyping and pilot production, system adaptation support, and manufacturing delivery from low-volume to complete machines.

Product Technical Highlights

System Design — Integrated 2× Gigabit Ethernet, USB 3.0 Type-C, M.2 SSD, TF, and serial ports; completed mechanical, fan thermal, EMC, and reliability design in one pass. Core board designed for LPDDR5 high-speed requirements with stack-up and impedance control to ensure stable compute and video pipeline throughput. Debian system optimization, driver porting, and video pipeline tuning based on RV64GC platform; supports H.265 8K@50fps or 32-channel 1080P@30fps decoding, concurrently running with 19.95 TOPS local inference.

Process Manufacturing — Provided PCB/PCBA prototyping and pilot verification; full-load burn-in, thermal, and drop testing; supports smooth transition from low-volume delivery to complete machine mass production.

Customer Value

Performance delivered: from "working" to sustained full-load — Runs local inference and multi-channel decoding at full capacity under ≤30W PoE powered, fan-equipped form factor. Power and thermal bottlenecks solved upfront in design phase; products can be directly deployed 7×24 in smart classrooms and conference venues.

Investment efficient: mass production without building your own hardware system — Hardware, mechanics, thermal, EMC, and manufacturing lines all handled in one pass; customer focuses on chip and algorithm layers. First prototype already meets mass production conditions, eliminating the cost of building teams, production lines, and trial-and-error.

Asset reusable: one capability set supports multi-scenario migration — The same complete machine platform, pilot verification, and reliability reports can be transferred to edge boxes, industrial PCs, smart analytics stations, and other scenarios; subsequent products do not need to repeat the full verification process.

Chips and ecosystem are in place. Leave the last mile of RISC-V to us.