Huawei Tau Scaling Law and the Time-Scaling Path for Post-Moore Semiconductors

A new semiconductor principle introduced in Shanghai

On May 25, 2026, the IEEE International Symposium on Circuits and Systems (ISCAS 2026) opened in Shanghai. The event normally belongs to the academic world of circuits, devices, and system architecture, yet one keynote drew attention far beyond the conference venue. He Tingbo, Huawei board member and president of Huawei's semiconductor business unit, presented a talk titled Exploration and Practice of New Semiconductor Paths and formally introduced the Tau Scaling Law.

The market reaction was immediate. On the same day, China's semiconductor supply chain moved sharply, with the STAR 50 Index rising 5.88% and SMIC's A-share price jumping 18.78%. Market movement alone does not validate a technical framework, although it does show how strongly the industry is looking for alternatives to the old scaling path. Huawei also stated that it has designed and mass-produced 381 chips over the past six years under this technical framework, covering communications, computing, and consumer electronics products. That production record gives the concept a degree of engineering weight that a purely academic proposal would not have.

Tau Scaling Law matters because it tries to answer a question that the semiconductor industry has been postponing for years: once shrinking transistors becomes too expensive, too slow, or too restricted by physics, where else can performance come from? Huawei's answer is to focus less on physical dimensions and more on time. In practical engineering terms, that means reducing delay across transistors, circuits, chiplets, packages, boards, and systems rather than relying only on smaller process nodes.

Geometric scaling is reaching both physical and economic limits

In 1965, Gordon Moore observed that the number of transistors on an integrated circuit was doubling at a roughly regular cadence. The statement later became known as Moore's Law and served as the operating rhythm for the semiconductor industry for more than half a century. Its core mechanism was geometric scaling: shrink the physical dimensions of transistors, place more of them in the same area, improve performance, and reduce cost per transistor. That path took the industry from micron-scale devices to 28nm, 7nm, 3nm, and now the early discussion of 2nm-class nodes.

The difficulty is that physics no longer provides the same room for movement. As transistor dimensions approach the scale of individual atoms, quantum tunneling becomes harder to suppress, leakage current rises, and heat removal becomes more difficult. At the manufacturing level, the cost curve has also changed. EUV lithography systems from ASML now cost more than $300 million per tool, while a leading-edge 3nm fab requires investment measured in tens of billions of dollars. Industry estimates often place the wafer cost of 3nm at more than ten times that of mature 28nm processes. Each new node still brings value, but the marginal improvement per dollar is getting harder to justify.

The economic constraint is just as important as the physical one. Only a few companies can afford to pursue the most advanced process nodes at scale. For companies and regions that cannot access EUV tools or leading-edge foundry capacity, the traditional geometric path is effectively blocked. This is the context in which Huawei is positioning Tau Scaling Law: not as a rejection of advanced process technology, but as a second performance path for a world where not every design can depend on the next lithography node.

Tau Scaling Law shifts the performance target from space to time

The Greek letter tau, written as τ, is commonly used in circuit theory to represent a time constant. In a semiconductor context, it can be understood as the time required for a signal, device, circuit, or workload to move from one useful state to another. Tau Scaling Law uses this idea as a broad optimization target. Instead of asking only how to place more transistors into a smaller area, it asks how to reduce the time consumed by signal switching, data movement, synchronization, and system-level processing.

This shift changes the engineering conversation. A chip may contain enough compute units, yet still waste time because data travels through long interconnect paths, waits for synchronization, moves across inefficient chiplet links, or stalls in memory access. Reducing those delays can improve effective performance even when the underlying transistor size stays the same. In simplified terms, performance improves as τ becomes smaller. That relationship is not a complete chip design formula, but it is a useful way to describe where optimization effort should move in the post-Moore period.

Huawei's public explanation makes an important distinction: Tau Scaling Law is intended to run alongside Moore's Law, not replace it outright. Advanced nodes will continue to matter for products that can justify their cost and secure access to manufacturing capacity. At the same time, mature processes can be pushed further through 3D integration, chiplet architecture, shorter signal paths, asynchronous design, high-bandwidth interconnects, and advanced packaging. Huawei has claimed that this approach can deliver performance comparable to a 1.4nm-class process in certain scenarios, although such claims will need to be judged case by case once more technical detail becomes available.

Logic Folding changes the role of architecture before packaging begins

Logic Folding is the most distinctive concept in Huawei's Tau framework. In conventional chip design, logic cells are largely arranged across a two-dimensional plane, and signals travel through metal interconnects before completing a logical operation. Longer interconnects increase resistance-capacitance delay, and that delay can become a larger part of the performance budget as transistor switching improves. Logic Folding attempts to rearrange logic in three-dimensional space so critical signal paths become shorter.

This should not be confused with ordinary die stacking after design is finished. In many 3D packaging schemes, completed dies are stacked vertically, and the package provides the interconnect. Logic Folding moves the optimization earlier into the design stage by restructuring logic topology before the chip is built. The potential advantage is clear: reducing delay at the source is more effective than trying to recover timing margin later through packaging or board-level design.

The manufacturing reality is demanding. Once logic is reorganized vertically, engineers have to manage thermal gradients, local power density, alignment tolerance, and yield risk across a much more complex structure. Hybrid bonding pitch, through-silicon vias, redistribution layers, and local interconnect parasitics all become part of the performance equation. A minor alignment or bonding defect may not simply reduce yield; it can create timing variation or thermal hot spots that are difficult to debug once the device is sealed inside a package. For PCB and substrate suppliers, this kind of upstream architectural shift eventually appears as tighter I/O density, more demanding package substrates, and stricter power integrity requirements at the board interface.

Chiplets, 3D stacking, and optical interconnects raise the value of packaging and substrates

Tau Scaling Law is not built around one technique. Huawei describes a set of enabling technologies that includes Logic Folding, the Lingqu Bus, high-density optical interconnects, chiplet integration, and 3D stacking. These technologies operate at different layers of the system, but they share one goal: reducing the time consumed by data movement and signal propagation.

Chiplet integration is already one of the more mature pieces of this direction. A large SoC can be split into smaller functional dies, with each die manufactured on the process node best suited to its function. Compute dies may use an advanced process, while analog, I/O, or memory-related functions may remain on mature nodes. 3D stacking then shortens interconnect distance by moving selected functions vertically. Hybrid bonding, silicon interposers, high-density redistribution layers, TSVs, and HBM interconnects all become central to system performance rather than secondary packaging details.

The Lingqu Bus fits into this picture as a low-latency, high-bandwidth interconnect concept for communication inside and between chips. In a chiplet system, individual dies can be fast on their own while the complete system still underperforms because data movement is too slow. A bus or interconnect fabric with lower latency can reduce waiting time between functional blocks. That same logic explains why high-density optical interconnects are receiving attention. Electrical signaling becomes harder as rates rise because insertion loss, crosstalk, equalization complexity, and power consumption increase. Optical links can reduce some of those constraints, although bringing optical interconnects into package-level or chip-level environments introduces difficult coupling, alignment, thermal, and reliability problems.

A production transition in this area often exposes issues that architecture diagrams do not show. A chiplet module may pass early functional tests, then encounter margin loss during temperature cycling because substrate warpage changes contact pressure or micro-bump stress. A high-speed interposer design may look clean in simulation, yet require several substrate material and stack-up revisions once insertion loss and return loss are measured on real hardware. These are not unusual failures; they are the normal engineering cost of moving performance from transistor scaling into interconnect and packaging.

The impact extends into PCB design and high-speed system integration

As more performance depends on interconnect delay, the boundary between chip design, package design, substrate design, and PCB design becomes less forgiving. PCB suppliers do not implement Logic Folding directly, but they receive its downstream consequences. Higher I/O density, faster SerDes channels, denser power delivery, and more concentrated thermal loads all eventually reach the board.

Signal integrity is the first visible pressure point. At 112Gbps and above, impedance discontinuities, via stubs, copper roughness, dielectric loss, reference-plane breaks, and connector transitions can quickly consume eye-margin. Materials such as Panasonic Megtron 6 or Megtron 7, TUC high-speed laminates, and other low-loss systems are selected not only for low dissipation factor, but also for stable dielectric behavior across frequency and temperature. A board that passes at room temperature may still show marginal behavior after thermal cycling or under high-humidity aging if resin content, glass weave effect, or copper profile varies enough across batches.

Power integrity becomes equally sensitive. Logic Folding and 3D integration can raise local current density, while chiplet systems introduce multiple power domains with different transient behavior. The PCB power distribution network must maintain low impedance across a wide frequency range, and package-board co-design becomes more important because decoupling strategy is split across silicon, package, and board. If the anti-resonance peaks are not controlled, a workload transition can produce voltage noise that appears as timing failure, link instability, or sporadic system resets.

Thermal design also changes. A time-scaling architecture can reduce certain delays, yet the resulting power density may be harder to remove. Thick copper, embedded copper coins, metal-core structures, thermal vias, high-conductivity interface materials, and separated thermal-electrical paths will see broader use beyond traditional power electronics. The tradeoff is manufacturability. Heavy copper improves current and heat handling, but it can increase etching difficulty, resin starvation risk, and lamination stress. For high-layer-count boards, registration drift during sequential lamination can become a bigger yield risk than the headline layer count suggests.

What PCB suppliers should prepare for

For PCB suppliers, the practical response is not to market every product as post-Moore ready. The more useful approach is to build capability in the areas where time-scaling systems create measurable manufacturing requirements. High-speed stack-up design, Any-Layer HDI, back drilling, controlled-depth drilling, low-loss laminate handling, SI/PI simulation, thermal simulation, and DFM review will matter more as interconnect delay becomes part of the performance budget.

Engineering service also becomes part of the product. A customer designing a chiplet-based accelerator or a high-speed compute module may need a board supplier to join before the layout is locked. At that stage, the supplier can still influence via structure, breakout strategy, stack-up symmetry, impedance targets, material selection, copper balance, and manufacturability. After Gerber release, many of those decisions are already expensive to change. Experienced suppliers have seen this pattern repeatedly: the cheapest quote at prototype stage can become costly if the first build uncovers insertion loss, plating voids, BGA reliability issues, or thermal deformation that should have been caught in DFM review.

Kingbrother's capability set is relevant to this kind of demand because time-scaling systems require a mix of high-speed, high-density, and thermal-management know-how. Support for 112Gbps high-speed transmission, FR-4 boards up to 72 layers, Any-Layer HDI, rigid-flex boards, thick copper up to 18oz, metal substrates, and thermal-electrical separation gives customers a broader process base for early design decisions. The point is not that one supplier solves every post-Moore problem. The point is that PCB partners with mature process windows, simulation support, and fast prototype-to-production feedback will be more useful as system performance depends increasingly on interconnect behavior.

A new coordinate system for the post-Moore period

Tau Scaling Law is still new, and the industry will need more public technical detail, benchmark data, design tool support, and ecosystem participation before it can be judged as a widely accepted semiconductor principle. Logic Folding needs EDA support. Chiplets need standardized die-to-die interfaces. Optical interconnects need practical integration methods that can survive manufacturing, testing, and field use. These requirements cannot be solved by one company alone.

Even so, Huawei's proposal captures a direction that is already visible across the industry. Performance improvement is moving beyond transistor geometry and into architecture, packaging, interconnect, substrate, board design, and system-level timing. Advanced process nodes will remain important, but they will no longer be the only performance story. For PCB and substrate suppliers, that shift is significant: the board is becoming a more active part of the performance equation, and suppliers that can manage high-speed loss, power noise, thermal stress, and manufacturing variation will have a stronger position in the next generation of AI and high-performance computing hardware.